Field of the Invention
The present invention generally relates to the semiconductor integrated circuit technology, and more particularly to a substrate biasing circuit.
Recently, there has been a tendency for the amount of power consumed in integrated circuits used to semiconductor elements due to fine scaling and speeding up of semiconductor elements. There has also been a demand to reduce the power consumption due to increased applications of the integrated circuits to devices driven by a battery. In order to reduce the power consumption, it is attempted to reduce the power supply voltage of the integrated circuits. However, as the power supply voltage is reduced, a problem due to differences among the threshold voltages of the individual transistors becomes conspicuous.
It is very difficult to avoid the occurrence of the differences among the individual transistors due to variations in the conditions of the production process. As described above, the problem caused by the differences among the threshold voltages of the transistors becomes conspicuous when the power supply voltage is reduced. For example, if the power supply voltage is as comparatively high as 3.3 V and the threshold voltage is varied by +0.15 V, the circuit driving speed is reduced by approximately 5%. If the power supply voltage is as comparatively low as 1 V and the threshold voltage is varied by +0.15 V, the circuit driving speed is reduced by 200%. Further, variations in the threshold voltage causes problems such as an increase in the leakage current and an increase in the amount of power consumed when the circuits are in the standby state.
A proposal directed to solving the above problems is described in Japanese Laid-Open Patent Application No. 6-139779 (IPC G11C 11/413). The proposed technique is to detect the threshold voltages of MOS transistors and control the substrate bias so as to compensate for a deviation in the detected threshold voltages. As shown in FIG. 1, a CMOS inverter 100 made up of a P-channel MOS transistor and an N-channel MOS transistor is arranged to detect the threshold voltage of the CMOS inverter based on the threshold voltages of the MOS transistors. An input terminal 100a of the CMOS inverter and an output terminal 100b thereof are connected together. Hence, a constant voltage determined by the threshold voltages of the MOS transistors can be obtained at the output terminal 100b. The above constant voltage, that is, the threshold voltage of the CMOS inverter, is then compared with a given reference voltage by a comparator circuit not shown.
However, the above arrangement in which the input terminal 100a and output terminal 100b of the inverter 100 are short-circuited, the operating point of the inverter 100 is located at point a shown in FIG. 2, and a large amount of pass-through current flows in the CMOS inverter. The horizontal axis of the graph of FIG. 2 denotes the input voltage of the CMOS inverter 100, and the vertical axis thereof denotes the output voltage thereof. When the input voltage of the inverter 100 increases to Vthinv, the output voltage is changed from a high level to a low level. At this time, a large amount of the pass-through current flows in the inverter 100.